The present invention generally relates to integrated circuits (ICs), and more particularly, to a memory controller.
Many ICs include a processor, a memory controller, and a memory. The processor generates a clock signal and data. Then, during a write transaction, the processor stores the data in the memory by way of the memory controller. During a read transaction, the processor reads the data from the memory by way of the memory controller.
Improvements in semiconductor technology have led to an increase in the processing speed of the processors, i.e., the speed of the high frequency clock signal to the processor. A conventional memory controller samples the data at a sampling rate based on at least one of the rising and falling edges of the clock signal. However, during a read transaction, when the memory controller receives data, the data is unstable for an interval of time, which is referred to as a data skew time interval. After the elapse of the data skew time, the memory controller receives the data, which now should be stable and not have any errors.
When the data is stable, the memory controller waits for a set up time interval to elapse before it can accurately sample the data. A predetermined time interval equals a sum of the data skew time and the set up time. If the memory controller samples the read data before the predetermined time interval has elapsed, then the data may not include errors. Hence, the data sampling rate during a read transaction depends on the frequency of the clock signal and the predetermined time interval.
The time period of a sampling cycle is equal to a sum of the time period of the clock cycle and the predetermined time interval. The sampling rate is equal to an inverse of the time period of the sampling cycle. The time period of the sampling cycle is greater than the time period of the clock cycle. Hence, the sampling rate is less than the frequency of the clock signal, i.e., the memory controller reads data at a slower rate than the rate at which the processor operates. Thus, a delay is introduced in the operation of the processor.
In one known technique to avoid the aforementioned problem, the memory controller includes a clock generator and a control circuit to generate a first read clock signal at a first frequency and at least one training packet of data, respectively, where the first frequency is greater than the frequency of the clock signal generated by the processor. The memory controller generates the data training packet to determine the data skew time interval, and stores the training packet in the memory. When the processor generates a read transaction, the memory controller receives the training packet and samples the training packet using the first read clock signal. The memory controller detects an earliest and a latest transition of the training packet. Thus, the memory controller determines a time interval during which the sampled data is inaccurate, based on the earliest and latest transitions, i.e., the memory controller determines the data skew time interval. The memory controller generates a second read clock signal at a second frequency, based on the data skew time interval. The time period of the second read clock signal is greater than or equal to the data skew time interval. Then the memory controller samples the training packet using the second read clock signal and generates a sampled training packet. The memory controller checks whether the training packet has been accurately sampled by comparing the training packet with the sampled training packet. If the training packet has been accurately sampled, the memory controller knows that it can sample read data from the memory using the second read clock signal. However, if the training packet has not been accurately sampled, the memory controller re-determines the data skew time interval. This process is repeated until the read clock signal used can accurately sample the training packet. Since the time period of the read clock signal is based on only the data skew time interval and not on the sum of a time period of the clock signal and the data skew time, the rate at which the memory controller samples the read data is greater than the rate at which the conventional memory controller samples the read data. However, the memory controller may require multiple iterations to determine an appropriate read clock signal. Thus, the memory controller introduces a delay in the execution of the read transaction and consequently, a delay in the operation of the processor. Further, the clock generator increases the complexity and power consumption of the memory controller.
It would be advantageous to have a memory controller that generates a read clock signal to sample data stored in a memory, ensures that the data is sampled accurately at a high frequency without causing a significant increase in the complexity of the memory controller, and does not increase the power consumption of the memory controller.